1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a capacitor electrode structure in an integrated circuit, such as a DRAM (dynamic random-access memory) device, through a self-aligned process.
2. Description of Related Art
In a typical DRAM device, each single memory cell is composed of a transfer field effect transistor (TFET) and a data storage capacitor. Whether each DRAM cell stores a binary value of 1 or 0 is dependent on whether the data storage capacitor therein is fully charged or uncharged. For example, when the capacitor is fully uncharged, it represents the storage of the binary data 0 therein, whereas when fully charged, it represents the storage of the binary data 1 therein.
FIG. 1 is a schematic diagram showing the equivalent circuit structure of one single memory cell of a typical DRAM device. As shown, each DRAM cell includes a TFET T and a data storage capacitor C. The capacitor C is composed of two electrodes 100, and a dielectric layer 101 sandwiched between the two electrodes 100. The TFET T is formed in such a manner that its gate is connected to a word line WL, its source is connected to a bit line BL, and its drain is connected via the capacitor C to the ground. Whether the memory cell stores a binary data bit 0 or 1 is dependent on whether the capacitor C is fully charged or uncharged. Any access to the data stored in the capacitor C whether read or write, is controlled by the TFET T whose ON/OFF state is further controlled by the voltage state on the wordline WL.
Fundamentally, the charge retaining capability of the capacitor C is proportional to its capacitance. In principle, the capacitance can be increased in the following ways: (1) increasing the surface area of the electrodes of the capacitor C; (2) choosing a dielectric material with a large dielectric constant to form the dielectric layer 102; and (3) reducing the thickness of the dielectric layer 102. With the present technology, however, the dielectric material with the maximum dielectric constant has been used, and therefore, the second method is unfeasible until a new dielectric material is developed. The third method is also unfeasible since there is a limit to the thickness of the dielectric layer.
Therefore, only the first method is a feasible way to increase the capacitance of the data storage capacitor in a DRAM cell. Much research effort in the semiconductor industry is directed to the goal of finding new methods that can increase the surface area of one or both electrodes of the data storage capacitor. There are many conventional methods for doing this. However, most of them are quite complex in procedural steps, and therefore are very laborious and cost-ineffective to carry out.